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101 innovation drive san jose, ca 95134 www.altera.com av-5v1-1.3 volume 1: device overview and datasheet arria v device handbook document last updated for alte ra complete design suite version: document publication date: 11.1 february 2012 arria v device handbook volume 1: device overview and datasheet
? 2012 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix word s and logos are trademarks of alte ra corporation and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specificat ions in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no respon sibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet iso 9001:2008 registered
february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v chapter 1. overview for th e arria v device family arria v feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 arria v family plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 low-power serial transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?7 pma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 pcs support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 pcie gen1 and gen2 hard ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?10 fpga gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?10 external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?11 alm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 variable-precision dsp block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 dynamic and partial reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 clock networks and pll clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 enhanced configuration and configuration vi a protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 soc fpga with hps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 features of the hps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 system peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 hps-fpga axi bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 hps sdram controller subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 fpga configuration and processor booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 hardware and software development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?20 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?21 chapter 2. device datasheet for arria v devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 internal weak pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?29 memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?30 temperature sensing diode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?30 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?31 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?31 dqs logic block and memory output clock jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . 2?35
iv contents arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?36 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?36 configuration specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?37 por specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?37 jtag configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?37 fpp configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?38 dclk-to-data[] ratio (r) for fpp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?38 fpp configuration timing when dclk to data[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?38 fpp configuration timing when dclk to data[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?41 as configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?43 ps configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?44 remote system upgrades circuitry timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?46 user watchdog internal oscillator frequency specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?46 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?47 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?47 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?47 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?48 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?51 additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1
february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet chapter revision dates the chapters in this document, volume 1: device overview and datasheet, were revised on the following dates. where chapte rs or groups of chapters are available separately, part numbers are listed. chapter 1. overview for the arria v device family revised: february 2012 part number: av51001-1.3 chapter 2. device datasheet for arria v devices revised: february 2012 part number: av-51002-1.3
vi chapter revision dates arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet
av51001-1.3 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. arria v device handbook volume 1: device overview and datasheet february 2012 subscribe iso 9001:2008 registered 1. overview for the arria v device family built on the 28-nm low-power process technology, arria ? v devices offer the lowest power and lowest system cost for mainstre am applications. arria v devices include unique innovations such as the lowest static power in its class, the lowest power transceivers of any midran ge family, support for serial data rates up to 10.3125 gigabits per second (gbps), a powerf ul collection of integrated hard intellectual property (ip), and a power-op timized core architecture, making arria v devices ideal for the following applications: power sensitive wireless infrastructure equipment 20g/40g bridging, switching, and packet processing applications high-definition video processing and image manipulation intensive digital signal processing (dsp) applications arria v devices are available in the following variants: arria v gx?fpga with integrated 6-gbps transceivers, this variant provides bandwidth, cost, and power levels that are optimized for high-volume data and signal-processing applications. arria v gt?fpga with integrated 10-gbps transceivers, this variant provides enhanced high-speed serial i/o bandwidt h for cost-sensitive data and signal processing applications. arria v sx?system-on-a-chip (soc) fpga with integrated arria v fpga and arm ? -based hard processor system (hps). arria v st?soc fpga with integrated arria v fpga, arm-based hps, and 10-gbps transceivers. the arria v soc fpga variants feature an fp ga integrated with an hps that consists of a dual-core arm cortex?-a9 mpcore? proc essor, a rich set of peripherals, and a shared multiport sdram memory controller. the unique feature set in arria v devices was chosen to optimize power, cost, and performance. these features include a re designed adaptive logic module (alm), distributed memory, new 10-kbit (m10k) inte rnal memory blocks, variable-precision dsp blocks, and fractional clock synthesis phase-locked loops (p lls) with a highly flexible clocking network, all interconnected by a power-optimized multitrack routing architecture. february 2012 av51001-1.3
1?2 chapter 1: overview for the arria v device family arria v feature summary arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet arria v devices provide interface support flex ibility with up to 10-gbps transceivers, 1.25-gbps lvds , 1.333-gbps memory interfaces with low latency, and support for all mainstream single-ended and differential i/o standards, including 3.3 v. arria v devices also offer the lowest system cost by requiring only three power supplies to operate the devices and a thermal compos ite flip chip ball-grid array (bga) packaging option. arria v devices also support innovative features, such as configuration via protocol (cvp), partia l reconfiguration, and design security. arria v devices provide the power, features, and cost you require to succeed with your designs. with these innovations, arria v devices deliver ideal performance and capability for a wide range of applications. arria v feature summary table 1?1 lists the arria v device features. table 1?1. feature summary for arria v devices (part 1 of 3) feature details technology 28-nm tsmc low-power process technology lowest static power in its class (less than 800 mw for 500 k logic elements (les) at 85c junction under typical conditions) 1.1-v core nominal voltage lowest-power serial transceivers of any midrange fpga 611-mbps to 10.3125-gbps integrated transceivers transmit pre-emphasis and receiver equalization dynamic reconfiguration of individual channels fpga general-purpose i/os (gpios) 1.25-gbps lvds 667-mhz/1.333-gbps external memory interface on-chip termination (oct) 3.3-v support embedded transceiver hard ip custom implementation up to 10.3125 gbps pci express ? (pcie ? ) gen1 and gen2 gbps ethernet (gbe) and xaui physical coding sublayer (pcs) common public radio interface (cpri) pcs gigabit-capable passive optical network (gpon) pcs
chapter 1: overview for th e arria v device family 1?3 arria v feature summary february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet hps (arria v sx and st devices only) dual-core arm cortex-a9 mpcore processor. up to 800 mhz maximum frequency that supports symmetric and asymmetric multiprocessing interface peripherals?10/100/1000 ethernet media access control (mac), usb 2.0 on- the-go (otg) controller, quad spi flash controller, nand flash controller, and sd/mmc/sdio controller, uart, serial peripheral interface (spi), i2c interfaces, and up to 86 gpio interfaces system peripherals?general-purpose and watchdog timers, direct memory access (dma) controller, fpga configuration manager, and clock and reset managers on-chip ram and boot rom hps?fpga bridges?include the fpga-to-hps, hps-to-fpga, and lightweight hps-to- fpga bridges that allow the fpga fabric to master transactions to slaves in the hps, and vice versa fpga-to-hps sdram controller subsystem?provides a configurable interface to the multiport front end of the hps sdram controller arm coresight? jtag debug, trace port, and on-chip trace storage three fractional plls physical medium attachment (pma) with soft pcs 10gbase-r 9.8304-gbps cpri high-performance core fabric enhanced alm with four registers improved routing architecture to reduce congestion and improve compilation time variable-precision dsp blocks natively supports three-signal processing precision ranging from 9 x 9, 18 x 19, or 27 x 27 in the same dsp block 64-bit accumulator and cascade for systolic finite impulse responses (firs) embedded internal coefficient memory pre-adder/subtractor improves efficiency internal memory blocks m10k, 10 kbit with soft error correction code (ecc) memory logic array block (mlab), 640-bit distributed lutram?you can use up to 25% of the les as mlab memory hardened double data rate3 (ddr3) and ddr2 memory controllers high-resolution fractional plls integer mode and fractional mode precision clock synthesis, clock delay compensation, and zero delay buffering (zdb) clock networks 625-mhz global clock network global, quadrant, and peripheral clock networks unused clock networks can be powered down to reduce dynamic power table 1?1. feature summary for arria v devices (part 2 of 3) feature details
1?4 chapter 1: overview for the arria v device family arria v family plan arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet arria v family plan arria v devices offer various thermal composite flip chip bga packaging options with differing price and performance points. table 1?2 and table 1?3 list the arria v devices features. configuration partial and dynamic reconfigurations cvp configuration via hps serial and parallel flash interface enhanced advanced encryption standard (aes) design security features tamper protection remote system upgrade packaging thermal composite flip chip bga packaging multiple device densities with identical package footprints for seamless migration between different device densities lead, lead-free (pb-free), and rohs-compliant options table 1?1. feature summary for arria v devices (part 3 of 3) feature details table 1?2. maximum resource counts for arria v gx devices ? preliminary feature arria v gx device 5agxa1 5agxa3 5agxa5 5agxa7 5agxb1 5agxb3 5agxb5 5agxb7 alms 28,302 56,100 71,698 91,680 113,208 136,880 158,491 190,240 le (k) 75 148 190 242 300 362 420 504 m10k memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414 mlab memory (kbit) 463 873 1,173 1,448 1,852 2,098 2,532 2,906 block memory (kbit) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140 variable-precision dsp blocks 240 396 600 800 920 1,045 1,092 1,139 18 x 19 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,278 fractional plls (1) 10 10 12 12 12 12 16 16 gpio 480 480 544 544 704 704 704 704 lvds transmitter (tx) (2) 68 68 120 120 160 160 156 160 lvds receiver (rx) (2) 80 80 136 136 176 176 172 176 pcie hard ip blocks 1 1 2 2 2 2 2 2 hard memory controllers 2 2 4 4 4 4 4 4 notes to table 1?2 : (1) the total number of available fractional plls is a combination of general-pu rpose and transceiver plls. transceiver fraction al plls that are not used by the transceiver i/o can be used as general-purpose fractional plls. (2) for the lvds channels coun t for each package, refer to the high-speed differentia l i/o interfaces with dpa in arria v devices chapter.
chapter 1: overview for th e arria v device family 1?5 arria v family plan february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet table 1?3. maximum resource counts for arria v gt, sx, and st devices? preliminary feature arria v gt device arria v sx device arria v st device 5agtd3 5agtd7 5asxb3 5asxb5 5astd3 5astd5 alms 136,880 190,240 132,075 174,340 132,075 174,340 le (k) 362 504 350 462 350 462 m10k memory blocks 1,726 2,414 1,729 2,282 1,729 2,282 mlab memory (kb) 2,098 2,906 2,014 2,658 2,014 2,658 block memory (kb) 17,260 24,140 17,288 22,820 17,288 22,820 variable-precision dsp blocks 1,045 1,156 809 1,068 809 1,068 18 x 19 multipliers 2,090 2,312 1,618 2,186 1,618 2,186 fpga fractional plls (1) 12 16 tbd tbd tbd tbd hps plls (1) ? ? tbd tbd tbd tbd fpga gpio 704 704 528 528 528 528 hps i/o ? ? 216 216 216 216 lvds tx (2) 160 160 120 120 120 120 lvds rx (2) 176 176 120 120 120 120 pcie hard ip blocks 222222 hard memory controllers443333 hps memory controllers??1111 arm cortex?a9 mpcore processor ? ? dual-core dual-core dual-core dual-core notes to table 1?3 : (1) the total number of available fractional plls is a combination of general-pu rpose and transceiver plls. transceiver fraction al plls, when not used by the transcei ver i/o, can be used as a general-purpose fractional pll. (2) for the lvds channels coun t for each package, refer to the high-speed differentia l i/o interfaces with dpa in arria v devices chapter.
1?6 chapter 1: overview for the arria v device family arria v family plan arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 1?4 lists the arria v package plan. the package plan shows the gpio counts, the maximum number of 6-gbps transceivers available, and the maximum number of 10-gbps transceivers availa ble per density and package. various combinations of 6-gbps and 10-gbps transcei ver counts are available. table 1?4. package plan for arria v devices ? preliminary (1) varients devices f672 (27 mm) flip chip f896 (31 mm) flip chip f1152 (35 mm) flip chip f1517 (40 mm) flip chip gpio xcvr gpio (2) hps i/o xcvr gpio hps i/o xcvr gpio hps i/o xcvr arria v gx (3) 5agxa1 336 9 480 ? 12 ? ? ? ? ? ? 5agxa3 336 9 480 ? 12 ? ? ? ? ? ? 5agxa5 336 9 384 ? 18 544 ? 24 ? ? ? 5agxa7 336 9 384 ? 18 544 ? 24 ? ? ? 5agxb1 ? ? 384 ? 18 544 ? 24 704 ? 24 5agxb3 ? ? 384 ? 18 544 ? 24 704 ? 24 5agxb5 ? ? ? ? ? 544 ? 24 704 ? 36 5agxb7 ? ? ? ? ? 544 ? 24 704 ? 36 arria v gt (4) , (5) 5agtd3 ? ? 384 ? 12, 2 544 ? 12, 4 704 ? 12, 4 5agtd7 ? ? ? ? ? 544 ? 12, 4 704 ? 12, 8 arria v sx (3) 5asxb3 ? ? 178 216 12 350 216 18 528 216 30 5asxb5 ? ? 178 216 12 350 216 18 528 216 30 arria v st (4) , (5) 5astd3 ? ? 178 216 6, 2 350 216 12, 2 528 216 12, 6 5astd5 ? ? 178 216 6, 2 350 216 12, 2 528 216 12, 6 notes to table 1?4 : (1) the arrows indicate the package vertical migration capability. vertical migration allows you to migrate across device densit ies for devices having the same dedicated pins, co nfiguration pins, and power pins for a gi ven package. (2) in the f896 package, the pcie hard ip block on the right side of the 5agxa5, 5ag xa7, 5agxb1, 5agxb3, and 5agtd3 devices supp orts x1 for gen1 and gen2 data rates. (3) the transceiver counts listed are for 6-gbps transceivers. (4) the transceiver counts listed are for 6-gbps and 10-gbps tr ansceivers, respectively. (5) you can alternatively configure any pair of 10-gbps channels as six 6-gbps channe ls. for instance, you can alternatively con figure the 5agtd7 device in the f1517 packag e as eighteen 6-gbps and si x 10-gbps, twenty-four 6-gbps and four 10-gbps, or thirty 6-gbps and two 1 0-gbps channels.
chapter 1: overview for th e arria v device family 1?7 low-power serial transceivers february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet low-power serial transceivers arria v devices deliver the industry?s lowest power 10-gbps transcei vers at less than 140 mw and 6-gbps transceivers at le ss than 100 mw power consumption per channel. arria v transceivers are designed to be standard compliant for a wide range of protocols and data rates. the transceivers are positioned on the left and right outer edges of the device, as shown in figure 1?1 . figure 1?1. device chip overview for arria v devices (1) , (2) notes to figure 1?1 : (1) this figure represents an arria v device with transceivers. ot her arria v devices may have a diffe rent floor plan than the o ne shown here. (2) this figure is a graphical repr esentation of a top view of th e silicon die, which corresponds to a reverse view for flip chi p packages. general purpose i/os (lvds, memory interface) integrated multiport memory controllers integrated multiport memory controllers general purpose i/os (lvds, memory interface) transceiver pma transceiver pma hard pcs hard pcs pcie hard ip pcie hard ip fractional pll fractional pll alm variable-precision dsp blocks m10k internal memory blocks
1?8 chapter 1: overview for the arria v device family low-power serial transceivers arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet pma support to prevent core and i/o noise from coupling into the transceivers, the pma block is isolated from the rest of the chip, ensuring optimal signal integrity. the transceiver channels consist of the pma, pcs, and cl ock networks. you can also use the unused receiver pma channels as additional transmit plls. table 1?5 lists the transceiver pma features. pcs support the arria v core logic connects to the pcs thro ugh an 8-, 10-, 16-, 20-, 32-, or 40-bit interface, depending on the transceiver data rate and protocol. arria v devices contain pcs hard ip to support pcie gen1 and gen2, xaui, gbe, serial rapidio ? (srio), and cpri protocols. all othe r standard and proprietary protocols from 611 mbps to 6.5536 gbps are supported through the custom double-width mode (up to 6.5536 gbps) and custom single-width mode (up to 3.75 gbps) transceiver pcs hard ip. a dedicated 80-bit interface to the core logic connects directly from the pma, bypassing the pcs hard ip, to support all protocols beyond 6.5536 gbps up to 10.3125 gbps. table 1?6 lists the transceiver pcs features. table 1?5. transceiver pma features for arria v devices features capability backplane support up to 16? fr4 pcb fabric drive capability at up to 6.5536 gbps chip-to-chip support up to 10.3125 gbps pll-based clock recovery superior jitter tolerance programmable serializer and deserializer (serdes) flexible serdes width equalization and pre-emphasis up to 6 db of pre-emphasis and 4 db of equalization ring oscillator transmit plls 611 mbps to 10.3125 gbps input reference clock range 27 mhz to 710 mhz transceiver dynamic reconfiguration allows reconfiguration of single channels without affecting operation of other channels table 1?6. transceiver pcs features for arria v devices (part 1 of 2) pcs support (1) data rates (gbps) transmitter data path receiver data path custom single- and double-width modes 0.61 to ~6.5536 phase compensation fifo, byte serializer, and 8b/10b encoder word aligner, 8b/10b decoder, byte deserializer, and phase compensation fifo pcie gen1: x1, x2, x4, x8 pcie gen2: x1, x2, x4 (2) 2.5 and 5.0 the same as custom single- and double-width modes, plus pipe 2.0 interface to the core logic the same as custom single- and double-width modes, plus rate match fifo and pipe 2.0 interface to the core logic gbe 1.25 the same as custom single- and double-width modes the same as custom single- and double-width modes, plus rate match fifo
chapter 1: overview for th e arria v device family 1?9 low-power serial transceivers february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet xaui 3.125 the same as custom single- and double-width modes, plus the xaui state machine for bonding four channels the same as custom single- and double-width modes, plus the xaui state machine for realigning four channels, and deskew fifo circuitry srio 1.25 to 6.25 the same as custom single- and double-width modes the same as custom single- and double-width modes sdi 0.27 (3) , 1.485, 2.97 phase compensation fifo, byte serializer byte deserializer and phase compensation fifo serial ata 1.5, 3.0, 6.0 phase compensation fifo, byte serializer, 8b/10b encoder phase compensation fifo, byte deserializer, word aligner, and 8b/10b decoder cpri (4) 0.6144 to 6.144 the same as custom single- and double-width modes, plus the tx deterministic latency the same as custom single- and double-width modes, plus the rx deterministic latency gpon (5) 1.25 and 2.5 phase compensation fifo and byte serializer phase compensation fifo and byte deserializer notes to table 1?6 : (1) data rates above 6.5536 gbps up to 10.3125 gbps, such as 10gbas e-r, are supporte d through soft pcs. (2) pcie gen2 is supported with the pcie hard ip only. (3) the 0.27-gbps data rate is supported using oversampling user logics that you must im plement in the fpga fabric. (4) cpri data rates above 6.5536 gbps, such as 9.8304 gbps, are supported through soft pcs. (5) the gpon standard does not support burst mode. table 1?6. transceiver pcs features for arria v devices (part 2 of 2) pcs support (1) data rates (gbps) transmitter data path receiver data path
1?10 chapter 1: overview for the arria v device family pcie gen1 and gen2 hard ip arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet pcie gen1 and gen2 hard ip arria v devices contain pcie hard ip designed for performance, ease-of-use, and increased functionality. the pcie hard ip consists of the phy mac, data link, and transaction layers. the pcie hard ip suppo rts pcie gen2 end point and root port for up to x4 lane configurations, and pcie gen1 end point and root port for up to x8 lane configurations. pcie endpoint support includes multifunct ion support for up to eight functions, as shown in figure 1?2 . the arria v pcie hard ip operates independ ently from the core logic, which allows the pcie link to wake up and complete link training in less than 100 ms, while the arria v device completes loading the programming file for the rest of the device. in addition, the arria v pcie hard ip has improved end-to-end data path protection using ecc. fpga gpios arria v devices offer highly configurable gpios. the following list describes the many features of the gpios: programmable bus hold and weak pull-up. lvds output buffer with programmabl e differential output voltage (v od ) and programmable pre-emphasis. dynamic on-chip parallel termination (r t oct) for all i/o banks with oct calibration to limit the termination impedance variation. on-chip dynamic termination to swap betw een serial and parallel termination, depending on whether there is reading or writing on a common bus for signal integrity. configurable unused voltage reference ( vref ) pins as user i/os. easy timing closure support using the hard ened read fifo in the input register path, and delay-locked loop (dll) delay chain with fine and coarse architecture. figure 1?2. pcie multifunction for arria v devices host cpu root complex memory controller local periph 1 local periph 2 pcie rp pcie link pcie ep fpga can gbe ata bridge to pcie sp1 gpio 12c usb
chapter 1: overview for th e arria v device family 1?11 external memory february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet external memory arria v devices support up to four hardened memory controllers for ddr3 and ddr2 sdram. each controller supports 8- to 32-bit components up to 4 gigabits (gb) in density with two-chip select and opti onal ecc. arria v devices do not support ddr3 sdram leveling. arria v devices also support soft memory controllers for ddr3, ddr2, lpddr2, and lpddr sdram, rldram ii, qdr ii, and qdr ii+ sram for maximum flexibility. table 1?7 lists the external memory interface block performance. table 1?7. external memory interface performance for arria v devices interface voltage (v) hard controller (mhz) soft controller (mhz) ddr3 sdram 1.5 533 667 1.35 533 667 1.25 400 400 ddr2 sdram 1.8 400 400 1.5 400 400 rldram ii 1.8 (1) 400 qdr ii+ sram 1.8 (1) 400 1.5 (1) 400 qdr ii sram 1.8 (1) 400 1.5 (1) 400 ddr ii+ sram (2) 1.8 (1) 400 1.5 (1) 400 lpddr sdram (2) 1.8 (1) 200 lpddr2 sdram (2) 1.2 (1) 400 notes to table 1?7 : (1) these memory interfaces are not suppor ted in the hard memory controller. (2) these memory interfaces are not available as altera ? ip.
1?12 chapter 1: overview for the arria v device family alm arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet alm arria v devices use a 28-nm alm as the basic building block of the device fabric. the alm shown in figure 1?3 uses an 8-input fracturable look-up table (lut) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. you can configure up to 25% of the alms in arria v devices as distributed mlabs. for more information, refer to ?embedded memory? on page 1?14 . variable-precision dsp block arria v devices feature a variable-precisi on dsp block that you can configure to support signal processing with precision ranging from 9 x 9, 18 x 19, and 27 x 27 bits natively. you can independently configure each dsp bl ock during compilation as a triple 9 x 9, a dual 18 x 19 multiply, or a single 27 x 27. with a dedicated 64-bit cascade bus, you can cascade multiple variable-precision dsp blocks to implement even higher precision dsp functions efficiently. the variable precision dsp block also supports these features: 64-bit accumulator that is the largest in the industry, double accumulator hard pre-adder that is available in both 18- and 27-bit modes cascaded output adders for efficient systolic fir filters dynamic coefficients 18-bit internal coefficient register banks enhanced independent multiplier operation efficient support for single floating point arithmetic inferability of all modes by th e altera complete design suite figure 1?3. alm for arria v devices adaptive lut full adder reg reg full adder reg reg 1 2 3 4 5 6 7 8
chapter 1: overview for th e arria v device family 1?13 variable-precision dsp block february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet table 1?8 lists the accommodation of different configurations in a dsp block. table 1?9 lists the number of multipliers in arria v devices. table 1?8. variable-precision dsp block configurations for arria v devices multiplier size (bit) dsp block resources expected usage three 9 x 9 1 variable-precision dsp block low precision fixed point for video applications two18 x 19 1 of variable-precision dsp block medium precision fixed point in fir filters two 18 x 19 with accumulate 1 variable-precision dsp block fir filters one 27 x 27 1 variable-precision dsp block single precision floating point table 1?9. number of multipliers in arria v devices variants devices variable precision dsp blocks independent input and output multiplications operator 18 x 19 multiplier adder mode 18 x 18 multiplier adder summed with 36-bit input 9x9 multipliers 18 x 19 multipliers 27 x 27 multipliers arria v gx 5agxa1 240 720 480 240 240 240 5agxa3 396 1,188 792 396 396 396 5agxa5 600 1,800 1,200 600 600 600 5agxa7 800 2,400 1,600 800 800 800 5agxb1 920 2,760 1,840 920 920 920 5agxb3 1,045 3,135 2,090 1,045 1,045 1,045 5agxb5 1,092 3,276 2,184 1,092 1,092 1,092 5agxb7 1,139 3,417 2,278 1,139 1,139 1,139 arria v gt 5agtd3 1,045 3,135 2,090 1,045 1,045 1,045 5agtd7 1,139 3,417 2,278 1,139 1,139 1,139 arria v sx 5asxb3 809 2,427 1,618 809 809 809 5asxb5 1,068 3,204 2,136 1068 1,068 1,068 arria v st 5astd3 809 2,427 1,618 809 809 809 5astd5 1,068 3,204 2,136 1068 1,068 1,068
1?14 chapter 1: overview for the arria v device family embedded memory arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet embedded memory the arria v memory blocks are flexible an d designed to provide an optimal amount of small- and large-sized memory arrays. arria v devices contain two types of embedded memory blocks: 640-bit mlab blocks?for wide and shallow memories. you can use up to 25% of the device labs as mlab. the mlab operates at up to 500 mhz. 10-kb m10k blocks?for larger memory configurations. the m10k embedded memory operates at up to 400 mhz. table 1?10 lists the supported memory configurations for arria v devices. dynamic and partial reconfiguration dynamic reconfiguration enables transceiver data rates or encoding schemes to be changed dynamically while maintaining da ta transfer on adjacent transceiver channels in arria v devices. dynamic reconfiguration is ideal for applications requiring on-the-fly multi-protocol or mu lti-rate support. you can reconfigure the pma, pcs, and pcie hard ip bloc ks with dynamic reconfiguration. partial reconfiguration allows you to reconfigure part of the device while other sections remain running. partial reconfigur ation is required in systems where the uptime is critical because it allows you to make updates or adjust functionality without disrupting other services. wh ile lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place the device functions that do not oper ate simultaneously. instead, you can store these functions in external memory and load them as required. this reduces the size of the required device by allowing multiple applications on a single device, which saves board space and reduces power consumption. altera simplifies the time-int ensive task of partial reconfiguration by building the partial reconfiguration capability on to p of the proven incremental compile and design flow in the quartus ? ii software. with this altera solution, you do not need to know all the intricate device architecture details to perform a partial reconfiguration. partial reconfiguration is supported throug h the fpp x16 configuration interface. you can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to enable partial reconfiguration of both the core and transceiver simultaneously. table 1?10. embedded memory block configuration for arria v devices memory block depth (bits) programmable widths mlab 32 x16, x18, or x20 m10k 256 x40 or x32 512 x20 or x16 1k x10 or x8 2k x5 or x4 4k x2 8k x1
chapter 1: overview for th e arria v device family 1?15 clock networks and pll clock sources february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet clock networks and pll clock sources the arria v clock network architecture is ba sed on altera?s proven global, quadrant, and peripheral clock structure, which is supported by dedicated clock input pins and fractional plls. arria v devices have 16 global clock networks capable of up to 625 mhz operation. the quartus ii software id entifies all unused se ctions of the clock network and powers them down, wh ich reduces power consumption. arria v devices have up to 16 plls with 18 output counters per pll. one fractional pll can use up to 18 output counters and two adjacent fractional plls share the 18 output counters. you can use fractional pl ls to reduce the number of oscillators required on your board, as well as reduce the clock pins used in the device by synthesizing multiple clock frequencies from a single reference clock source. you can use the plls for frequency synthesis, on -chip clock deskew, jitter attenuation, dynamic phase-shift, zero delay buffers, counters reconfiguration, bandwidth reconfiguration, programmable output cl ock duty cycles, pll cascading, and reference clock switchover. arria v devices use a fractional pll architectu re in addition to the historical integer pll. when you use fractional pll mode, you can use the plls for precision fractional-n frequency synthe sis?removing the need for an off-chip reference clock. transceiver fractional plls, when not used by the transceiver i/o, can be used as general-purpose fractional plls by the fpga fabric.
1?16 chapter 1: overview for the arria v device family enhanced configuration and configuration via protocol arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet enhanced configuration and co nfiguration via protocol arria v devices support 3.3-v programming voltage and the following configuration modes: active serial (as) passive serial (ps) fast passive parallel (fpp) cvp configuration via hps configuration through jtag you can configure arria v devices through pcie using cvp instead of an external flash or rom. the cvp mode offers the fast est configuration rate and flexibility with the easy-to-use pcie hard ip block inte rface. the arria v cvp implementation conforms to the pcie 100-ms power-up-to-active time requirement. f for more information regarding cvp, refer to the configuration via protocol (cvp) implementation in al tera fpgas user guide . table 1?11 lists the configuration modes that arria v devices support. power management arria v devices leverage fpga architectural features and process technology advancements to reduce the total device co re power consumption by as much as 50% when compared with stratix iv devices at the same performance level. additionally, arria v devices have a number of hard ip blocks that not only reduce logic resources but also deliver substantial power savings when compared with soft implementations. the list includes pcie gen1 and gen2, xaui, gbe, srio, gpon and cpri protocols. the hard ip blocks consume up to 25% less power than equivalent soft implementations. table 1?11. configuration modes and features for arria v devices mode data width (bit) maximum clock rate (mhz) maximum data rate (mbps) decompression design security remote system update partial reconfiguration as 1, 4 100 ? vvv ? ps 1 125 125 vv ?? fpp 8, 16 125 ? vv parallel flash loader 16-bit only cvp x1, x2, x4, x8 (1) ?? vvv v hps 32 125 ? vv parallel flash loader v jtag 1 33 33 ? ? ? ? note to table 1?11 : (1) number of lanes instead of bits.
chapter 1: overview for th e arria v device family 1?17 soc fpga with hps february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet arria v transceivers are also designed for power efficiency. as a result, the transceiver channels consume 50% less power than the previous generation of arria devices. soc fpga with hps each soc fpga device combines an fpga fa bric and an hps in a single device. this combination delivers the flexibility of programmable logic with the power and cost savings of hard ip in the following ways: reduces board space, system power, and bi ll of materials cost by eliminating a discrete embedded processor allows you to differentiate the end prod uct in both the hardware and software, and to support virtually any interface standard extends the product life and revenue th rough in-field hardware and software updates features of the hps the hps consists of a dual-core arm cort ex-a9 mpcore processor, a rich set of peripherals, and a shared multiport sd ram memory controller, as shown in figure 1?4 .. figure 1?4. hps with dual-core arm cortex-a9 mpcore processor fpga fabric hps hps-to-fpga lightweight hps-to-fpga fpga-to-hps fpga-to-hps sdram configuration controller fpga manager 64 kb on-chip ram 64 kb boot rom level 3 interconnect ethernet mac (2x) usb otg (2x) nand flash controller sd/mmc/sdio controller dma controller etr (trace) debug access port arm cortex-a9 mpcore cpu0 (arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit) cpu1 (arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit) scu acp l2 cache (512 kb) multiport ddr sdram controller with optional ecc low speed peripherals (timers, gpios, uart, spi, i2c, quad spi flash controller, system manager, clock manager, reset manager, and scan manager)
1?18 chapter 1: overview for the arria v device family soc fpga with hps arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet system peripherals the ethernet mac, usb otg controller, nand flash controller and sd/mmc/sdio controller modules have an integrated dma controller. for modules without an integrated dma controller, an additional dma controller module provides up to eight channels for high-bandwidth data tr ansfers. the debug access port provides interfaces to industry standard jtag debug probes and supports arm coresight debug and core traces to facilitate software development. hps-fpga axi bridges the hps?fpga bridges, which suppor t the advanced mi crocontroller bus architecture (amba ? ) advanced extensible interface (axi ? ) specifications, consist of the following bridges: fpga-to-hps axi bridge?a high-performance bus supporting 32-, 64-, and 128-bit data widths that allows the fpga fa bric to master transactions to the slaves in the hps hps-to-fpga axi bridge?a high-performance bus supporting 32-, 64-, and 128-bit data widths that allows the hps to master transactions to the slaves in the fpga fabric. lightweight hps-to-fpga axi bridge?a lower performance 32-bit width bus that allows the hps to master transactions to the slaves in the fpga fabric. the hps?fpga axi bridges also allow the fpga fabric to access the memory shared by one or both microprocessors, and prov ide asynchronous clock crossing with the clock from the fpga fabric. hps sdram controller subsystem the hps sdram controller subsystem cont ains a multiport sdram controller and ddr phy that is shared between the fpga fabric (through the fpga-to-hps sdram interface), the level 2 (l 2) cache, and the le vel 3 (l3) system interconnect. the fpga-to-hps sdram interface supports amba axi and avalon ? memory-mapped (avalon-mm) interface standards, and provides up to four ports with separate read and write directions. to maximize memory performance, the hp s sdram controller subsystem supports command and data reordering, deficit ro und-robin arbitration with aging, and high-priority bypass features. the hps sdram controller subsystem supports ddr2, ddr3, lpddr, or lpddr2 devices up to 4 gb and runs up to 533 mhz (1066 mbps data rate). for easy migration, the fpga-to-hps sdram interface is compatible with the interface of the soft sdram memory controller ips and hard sdram memory controllers in the fpga fabric. fpga configuration and processor booting the fpga fabric and hps in the soc fpga are powered independently. you can reduce the clock frequencies or gate the cl ocks to reduce dynamic power, or shut down the entire fpga fabric to reduce total system power. you can configure the fpga fabric and boot the hps independently, in any order, providing you with more design flexibility:
chapter 1: overview for th e arria v device family 1?19 soc fpga with hps february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet you can boot the hps before you power up and configure the fpga fabric. after the system is running, the hps reconfigur es the fpga fabric at any time under program control or through the fpga configuration controller. you can power up both the hps and the fpga fabric together, configure the fpga fabric first, and then upload the boot code to the hps from the fpga fabric. hardware and software development for hardware development, you can configure the hps and connect your soft logic in the fpga fabric to the hps interfaces usin g the qsys system integration tool in the quartus ii software. for software development, the arm-base d soc fpga devices inherit the rich software development ecosystem available for the arm cortex-a9 mpcore processor. the software development process for altera soc fpgas follows the same steps as those for other soc devices. altera also provides support for the linux and vxworks ? operating systems. you can begin device-specifi c firmware and software development on the altera soc fpga virtual target. the virtual target is a pc-based fast-functional simulation of a target development system?a model of a complete development board that runs on a pc. the virtual target enables the de velopment of device-specific production software that can run unmodified on actual hardware.
1?20 chapter 1: overview for the arria v device family ordering information arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet ordering information this section describes the ordering information for arria v devices. figure 1?5 and figure 1?6 show the ordering codes for arria v devices. figure 1?5. ordering information for arria v gx and gt devices gx variant a1: 75k logic elements a3: 149k logic elements a5: 190k logic elements a7: 243k logic elements b1: 300k logic elements b3: 362k logic elements b5: 420k logic elements b7: 503k logic elements gt variant d3: 362k logic elements d7: 503k logic elements family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method gx : 6-gbps transceivers gt : 10-gbps transceivers b : no hard pcie or hard memory controller m : 1 hard pcie and 2 hard memory controller f : maximum 2 hard pcie and 4 hard memory controllers 5a : arria v d : 9 e : 12 g : 18 h : 24 k : 36 f : fineline bga (fbga) fbga package type 27 : 672 pins 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) n : lead-free packaging es : engineering sample 5a gx m a5 g 4 f 31 c 4 n member code family variant gx variant 4 : 6-gbps 6 : 3-gbps gt variant 3 : 10-gbps gx variant 4 (fastest) 5 6 gt variant 5
chapter 1: overview for th e arria v device family 1?21 document revision history february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet document revision history table 1?12 lists the revision history for this chapter. figure 1?6. ordering information for arria v sx and st devices family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method sx : 6-gbps transceivers st : 10-gbps transceivers b : no hard pcie or hard memory controller m : 1 hard pcie and 2 hard memory controller f : maximum 2 hard pcie and 3 hard memory controllers (these numbers do not include the hard memory controllers in the hps) sx variant b3 : 350k logic elements b5 : 460k logic elements st variant d3 : 350k logic elements d5 : 460k logic elements 5a : arria v sx variant (6-gbps) d : 9 e : 12 g : 18 h : 24 st variant (6-gbps, 10-gbps) e : 6, 2 g : 18, 2 k : 12, 6 sx variant 4 : 6-gbps 6 : 3-gbps st variant 3 : 10-gbps f : fineline bga (fbga) fbga package type 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) sx variant 4 (fastest) 5 6 st variant 5 n : lead-free packaging es : engineering sample 5a st f d5 k 4 f40 i5 n member code family variant table 1?12. document revision history date version changes february 2012 1.3 updated table 1?2 and table 1?3 . updated figure 1?5 and figure 1?6 . minor text edits. december 2011 1.2 minor text edits. november 2011 1.1 updated table 1?1, table 1?2, table 1?3, table 1?4, table 1?6, table 1?7, table 1?9, and table 1?10. added ?soc fpga with hps? section. updated ?clock networks and pll clock sources? and ?ordering information? sections. updated figure 1?5. added figure 1?6. minor text edits. august 2011 1.0 initial release.
1?22 chapter 1: overview for the arria v device family document revision history arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet
av-51002-1.3 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. arria v device handbook volume 1: device overview and datasheet february 2012 subscribe iso 9001:2008 registered 2. device datasheet for arria v devices this chapter describes the electrical charac teristics, switching characteristics, and configuration specifications for arria ? v devices. electrical characteristics include operating conditions and power consumption. switching characteristics include transceiver specifications, and core an d periphery performance. configuration specifications include power-on reset (por) specification, initialization clock source option and timing, various configuration mode timing parameters, remote system upgrades timing, and user watchdog internal oscillator frequency specification. this chapter also describes i/o timing, including programmable i/o element (ioe) delay and programmable output buffer delay. f for more information about the densities and packages of devices in the arria v family, refer to the overview for arria v device family chapter. electrical characteristics the following sections describe the electrical characteristics of arria v devices. operating conditions when you use arria v devices, they ar e rated according to a set of defined parameters. to maintain the highest possible performance and reliability of the arria v devices, you must consider the operating requirements described in this chapter. arria v devices are offered in commercial and industrial grades. commercial devices are offered in ?4 (fastest), ?5, and ?6 speed grades. industrial grade devices are offered in the ?5 speed grade. absolute maximum ratings absolute maximum ratings define the ma ximum operating conditions for arria v devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. february 2012 av-51002-1.3
2?2 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet c conditions other than those listed in table 2?1 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have ad verse effects on the device. table 2?1. absolute maximum ratings for arria v devices? preliminary symbol description minimum maximum unit v cc core voltage power supply ?0.5 1.35 v v ccp periphery circuitry, pcie ? hard ip block, and transceiver physical coding sublayer (pcs) power supply ?0.5 1.35 v v ccpgm configuration pins power supply ?0.5 3.75 v v ccaux auxiliary supply ?0.5 3.75 v v ccbat battery back-up power supply for design security volatile key register ?0.5 3.75 v v ccpd i/o pre-driver power supply ?0.5 3.75 v v ccio i/o power supply ?0.5 3.9 v v ccd_fpll phase-locked loop (pll) digital power supply ?0.5 1.8 v v cca_fpll pll analog power supply ?0.5 3.75 v v cca_gxb transceiver high voltage power ?0.5 3.75 v v cch_gxb transmitter output buffer power ?0.5 1.8 v v ccr_gxb receiver power ?0.5 1.21 v v cct_gxb transmitter power ?0.5 1.21 v v ccl_gxb clock network power ?0.5 1.21 v v i dc input voltage ?0.5 4 v i out dc output current per pin ?25 40 ma t j operating junction temperature ?55 125 c t stg storage temperature (no bias) ?65 150 c v cc_hps core voltage power supply ?0.5 1.35 v v ccpd_hps i/o pre-driver power supply ?0.5 3.75 v v ccio_hps i/o power supply ?0.5 3.9 v v ccrstclk_hps configuration pins power supply ?0.5 3.75 v v ccpll_hps pll analog power supply ?0.5 3.75 v
chapter 2: device datasheet for arria v devices 2?3 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage listed in table 2?2 and undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. table 2?2 lists the maximum allowed input oversh oot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percenta ge of high time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 3.95 v can only be at 3.95 v fo r ~5% over the lifetime of the device; for a device lifetime of 10 years, this amounts to half a year. table 2?2. maximum allowed overshoot during transitions for arria v devices? preliminary symbol description condition (v) overshoot duration as % of high time unit vi (ac) ac input voltage 3.7 100 % 3.75 59.79 % 3.8 33.08 % 3.85 18.45 % 3.9 10.36 % 3.95 5.87 % 43.34% 4.05 1.92 % 4.1 1.11 %
2?4 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet recommended operating conditions this section lists the functional operation limits for the ac and dc parameters for arria v devices. table 2?3 lists the steady-state voltage values expected from arria v devices. power supply ramps must all be strictly monotonic, without plateaus. table 2?3. recommended operating conditions for arria v devices? preliminary symbol description condition minimum typical maximum unit v cc core voltage power supply ? 1.07 1.1 1.13 v v ccp periphery circuitry, pcie hard ip block, and transceiver pcs power supply ? 1.07 1.1 1.13 v v ccaux auxiliary supply ? 2.375 2.5 2.625 v v ccpd (1) i/o pre-driver (3.3 v) power supply ? 3.135 3.3 3.465 v i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.3 v) power supply ? 3.135 3.3 3.465 v i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.35 v) power supply ? 1.283 1.35 1.418 v i/o buffers (1.25 v) power supply ? 1.19 1.25 1.31 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.3 v) power supply ? 3.135 3.3 3.465 v configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_fpll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_fpll pll digital voltage regulator power supply ? 1.425 1.5 1.575 v v ccbat (2) battery back-up power supply (for design security volatile key register) ? 1.2?3.0v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c t ramp (3) power supply ramp time slow por (porsel=0) 200 s ? 100 ms ? fast por (porsel=1) 200 s ? 4 ms ? notes to table 2?3 : (1) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. (2) if you do not use the design security feature in arria v devices, connect v ccbat to a 1.5-v, 2.5-v or 3.0-v power supply. arria v por circuitry monitors v ccbat . arria v devices do not exit por if v ccbat stays low. (3) when power is applied to an arria v d evice, a por occurs if the po wer supply reaches the recomme nded operating range in the maximum power supply ramp.
chapter 2: device datasheet for arria v devices 2?5 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet table 2?4 lists the transceiver power supply recommended operating conditions for arria v devices. table 2?5 lists the steady-state voltage and cu rrent values expected from arria v system-on-a-chip (soc) fpga with arm ? -based hard processor system (hps). power supply ramps must all be strictly monotonic, without plateaus. table 2?4. transceiver power supply operating conditions for arria v gx and gt devices? preliminary symbol description minimum typical maximum unit v cca_gxbl transceiver high voltage power (left side) 2.375 2.5 2.625 v v cca_gxbr transceiver high voltage power (right side) v ccr_gxbl receiver power (left side) 1.07 1.1 1.13 v v ccr_gxbr receiver power (right side) v cct_gxbl transmitter power (left side) 1.07 1.1 1.13 v v cct_gxbr transmitter power (right side) v cch_gxbl transmitter output buffer power (left side) 1.425 1.5 1.575 v v cch_gxbr transmitter output buffer power (right side) v ccl_gxbl clock network power (left side) 1.07 1.1 1.13 v v ccl_gxbr clock network power (right side) 1.07 1.1 1.13 v table 2?5. hps power supply operating conditions for arria v sx and st devices? preliminary symbol description minimum typical maximum unit v cc_hps hps core voltage and periphery circuitry power supply 1.07 1.1 1.13 v v ccpd_hps hps i/o pre-driver (3.3 v) power supply 3.135 3.3 3.465 v hps i/o pre-driver (3.0 v) power supply 2.85 3.0 3.15 v hps i/o pre-driver (2.5 v) power supply 2.375 2.5 2.625 v v ccio_hps hps i/o buffers (3.3 v) power supply 3.135 3.3 3.465 v hps i/o buffers (3.0 v) power supply 2.85 3.0 3.15 v hps i/o buffers (2.5 v) power supply 2.375 2.5 2.625 v hps i/o buffers (1.8 v) power supply 1.71 1.8 1.89 v hps i/o buffers (1.5 v) power supply 1.425 1.5 1.575 v hps i/o buffers (1.2 v) power supply 1.14 1.2 1.26 v v ccrstclk_hps hps reset and clock input pins (3.3 v) power supply 3.135 3.3 3.465 v hps reset and clock input pins (3.0 v) power supply 2.85 3.0 3.15 v hps reset and clock input pins (2.5 v) power supply 2.375 2.5 2.625 v hps reset and clock input pins (1.8 v) power supply 1.71 1.8 1.89 v v ccpll_hps hps pll analog voltage regulator power supply 2.375 2.5 2.625 v
2?6 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet dc characteristics this section lists the supply current, i/o pin leakage current, input pin capacitance, on-chip termination tolerance, and hot socketing specifications. supply current standby current is the current drawn from the respective power rails used for power budgeting. use the excel-based early po wer estimator (epe) to estimate supply current for your design because these currents vary greatly with the resources you use. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . i/o pin leakage current table 2?6 lists the arria v i/o pin le akage current specifications. bus hold specifications table 2?7 lists the arria v device bus hold specifications. table 2?6. i/o pin leakage current for arria v devices? preliminary symbol description conditions min typ max unit i i input pin v i = 0 v to v cciomax ?30 ? 30 a i oz tri-stated i/o pin v o = 0 v to v cciomax ?30 ? 30 a table 2?7. bus hold parameters for arria v devices? preliminary (1) (part 1 of 2) parameter symbol conditions v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus-hold, low, sustaining current i susl v in > v il (max.) 8 ? 12 ? 30?50?70?70?a bus-hold, high, sustaining current i sush v in < v ih (min.) ?8 ? ?12 ? ?30 ? ?50 ? ?70 ? -70 ? a bus-hold, low, overdrive current i odl 0v < v in < v ccio ? 125 ? 175 ? 200 ? 300 ? 500 ? 500 a
chapter 2: device datasheet for arria v devices 2?7 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet (oct) specifications if you enable on-chip termination (oct) ca libration, calibration is automatically performed at power up for i/os connected to the calibration block. table 2?8 lists the arria v oct termination calibrat ion accuracy specifications. bus-hold, high, overdrive current i odh 0v < v in < v ccio ? -125 ? -175 ? -200 ? -300 ? -500 ? -500 a bus-hold trip point v trip ? 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 v note to table 2?7 : (1) the bus-hold trip points are based on calc ulated input voltages fr om the jedec standard. table 2?7. bus hold parameters for arria v devices? preliminary (1) (part 2 of 2) parameter symbol conditions v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max table 2?8. oct calibration accuracy specifications for arria v devices? preliminary (1) (part 1 of 2) symbol description conditions (v) calibration accuracy unit c4 c5, i5 c6 25- ? r s internal series termination with calibration (25- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 50- ? r s internal series termination with calibration (50- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 34- ? and 40- ? r s internal series termination with calibration (34- ? and 40- ? setting) v ccio = 1.5, 1.35, 1.25, 1.2 15 15 15 % 48- ??? 60- ??? and 80- ? r s internal series termination with calibration (48- ? , 60- ? , and 80- ? setting) v ccio = 1.2 15 15 15 % 50- ? r t internal parallel termination with calibration (50- ? setting) v ccio = 2.5, 1.8, 1.5, 1.2 ?10 to +40 ?10 to +40 ?10 to +40 % 20- ? , 30- ? , 40- ? ,60- ??? and 120- ? r t internal parallel termination with calibration (20- ? , 30- ? , 40- ? , 60- ? , and 120- ? setting) v ccio = 1.5, 1.35, 1.25 ?10 to +40 ?10 to +40 ?10 to +40 %
2?8 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet calibration accuracy for the calibrated on-chip series termination (r s oct) and on-chip parallel termination (r t oct) are applicable at the moment of calibration. when process, voltage, and temperature (p vt) conditions change after calibration, the tolerance may change. table 2?9 lists the arria v oct without calibr ation resistance tolerance to pvt changes. 60- ? and 120- ?? r t internal parallel termination with calibration (60- ? and 120- ? setting) v ccio = 1.2 ?10 to +40 ?10 to +40 ?10 to +40 % 25- ? r s_left_shift internal left shift series termination with calibration (25- ? r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % note to table 2?8 : (1) oct calibration accuracy is valid at the time of calibration only. table 2?8. oct calibration accuracy specifications for arria v devices? preliminary (1) (part 2 of 2) symbol description conditions (v) calibration accuracy unit c4 c5, i5 c6 table 2?9. oct without calibration resistance tolerance specifications for arria v devices? preliminary symbol description conditions (v) resistance tolerance unit c4 c5, i5 c6 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 3.0 and 2.5 30 40 40 % 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 1.8 and 1.5 30 40 40 % 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 1.2 35 50 50 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 3.0 and 2.5 30 40 40 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 1.8 and 1.5 30 40 40 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 1.2 35 50 50 % 100- ? r d internal differential termination (100- ? setting) v ccio = 2.5 25 tbd tbd %
chapter 2: device datasheet for arria v devices 2?9 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet oct calibration is automatically performed at power up for oct-enabled i/os. table 2?10 lists oct variation with temperature and voltage after power-up calibration. use table 2?10 to determine the oct variation after power-up calibration and equation 2?1 to determine the oct variation without recalibration. table 2?10 lists the oct variation after the power-up calibration. pin capacitance table 2?11 lists the arria v pin capacitance. equation 2?1. oct variation without recalibration? preliminary (1) , (2) , (3) , (4) , (5) , (6) notes to equation 2?1 : (1) the r oct value calculated from equation 2?1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) ? t is the variation of temperature with respect to the temperature at power up. (4) ? v is the variation of voltage with respect to the v ccio at power up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. table 2?10. oct variation after power-up calibration for arria v devices? preliminary (1) symbol description v ccio (v) value unit dr/dv oct variation of voltage without recalibration 3.0 0.0297 %/mv 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 dr/dt oct variation of temperature without recalibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 note to table 2?10 : (1) valid for a v ccio range of 5% and temperature range of 0 to 85c. table 2?11. pin capacitance for arria v devices symbol description value unit c iotb input capacitance on top/bottom i/o pins 5.5 pf c iolr input capacitance on left/right i/o pins 5.5 pf c outfb input capacitance on dual-purpose clock output/feedback pins 5.5 pf r oct r scal 1 dr dt ------ - ? t ? ?? dr dv ------- ? v ? ?? ? + ?? ?? =
2?10 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet hot socketing table 2?12 lists the hot socketing specifications for arria v devices. internal weak pull-up resistor table 2?13 lists the weak pull-up resistor values for arria v devices. table 2?12. hot socketing specifications for arria v devices? preliminary symbol description maximum i iopin (dc) dc current per i/o pin 300 ? a i iopin (ac) ac current per i/o pin 8 ma (1) i xcvr-tx (dc) dc current per transceiver transmitter (tx) pin 100 ma i xcvr-rx (dc) dc current per transceiver receiver (rx) pin 50 ma note to table 2?12 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate. table 2?13. internal weak pull-up resistor values for arria v devices? preliminary (1) , (2) symbol description conditions (v) (3) value (4) unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. v ccio = 3.3 5% 25 k ? v ccio = 3.0 5% 25 k ? v ccio = 2.5 5% 25 k ? v ccio = 1.8 5% 25 k ? v ccio = 1.5 5% 25 k ? v ccio = 1.35 5% 25 k ? v ccio = 1.25 5% 25 k ? v ccio = 1.2 5% 25 k ? notes to table 2?13 : (1) all i/o pins have an option to enable weak pull- up except the configuration, test, and jtag pins. (2) the internal weak pull-down feature is only available for the jtag tck pin. the typical value for this in ternal weak pull-down resistor is approximately 25 k ?? (3) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . (4) valid with 10% toleranc es to cover changes over pvt.
chapter 2: device datasheet for arria v devices 2?11 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet i/o standard specifications table 2?14 through table 2?19 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by arria v devices. the i/o standards tables also list the arria v device family i/o standard specifications. the v ol and v oh values are valid at the corresponding i oh and i ol , respectively. for an explanation of terms used in table 2?14 through table 2?19 , refer to ?glossary? on page 2?48 . table 2?14. single-ended i/o standards for arria v devices? preliminary i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min 3.3-v lvttl 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3-v lvcmos 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 2 ?2 3.0-v lvttl 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.4 2.4 2 ?2 3.0-v lvcmos 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 0.1 ?0.1 3.0-v pci 2.85 3 3.15 ? 0.3 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 2.5 v 2.375 2.5 2.625 ?0.3 0.7 1.7 3.6 0.4 2 1 ?1 1.8 v 1.71 1.8 1.89 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.45 v ccio ? 0.45 2 ?2 1.5 v 1.425 1.5 1.575 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 1.2 v 1.14 1.2 1.26 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 table 2?15. single-ended sstl and hstl i/o reference voltage specifications for arria v devices? preliminary (part 1 of 2) i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio v ref ? 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl 135 class i, ii 1.283 1.35 1.418 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl 125 class i, ii 1.19 1.25 1.26 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio
2?12 chapter 2: device datash eet for arria v devices electrical characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 x v ccio 0.5 x v ccio 0.53 x v ccio ?v ccio /2 ? hsul-12 1.14 1.2 1.3 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio ??? table 2?15. single-ended sstl and hstl i/o reference voltage specifications for arria v devices? preliminary (part 2 of 2) i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max table 2?16. single-ended sstl and hstl i/o standards signal specifications for arria v devices? preliminary (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i ?0.3 v ref ?0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.608 v tt + 0.608 8.1 ?8.1 sstl-2 class ii ?0.3 v ref ?0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.81 v tt + 0.81 16.2 ?16.2 sstl-18 class i ?0.3 v ref ?0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 v tt ? 0.603 v tt + 0.603 6.7 ?6.7 sstl-18 class ii ?0.3 v ref ?0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 0.28 v ccio ?0.28 13.4 ?13.4 sstl-15 class i ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 8?8 sstl-15 class ii ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 16 ?16 sstl 135 ? v ref ? 0.09 v ref + 0.09 ? v ref ? 0.16 v ref + 0.16 tbd (1) tbd (1) tbd (1) tbd (1) sstl 125 ? v ref ? 0.85 v ref + 0.85 ? v ref ? 0.15 v ref + 0.15 tbd (1) tbd (1) tbd (1) tbd (1) hstl-18 class i ? v ref ?0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-18 class ii ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-15 class i ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-15 class ii ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ?0.4 16 ?16 hstl-12 class i ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 8?8 hstl-12 class ii ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 16 ?16
chapter 2: device datasheet for arria v devices 2?13 electrical characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet hsul-12 ? v ref ? 0.13 v ref + 0.13 ? v ref ? 0.22 v ref + 0.22 0.1 x v ccio 0.9 x v ccio tbd (1) tbd (1) note to table 2?16 : (1) pending silicon characterization. table 2?16. single-ended sstl and hstl i/o standards signal specifications for arria v devices? preliminary (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min table 2?17. differential sstl i/o standards for arria v devices? preliminary i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 ? 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 ? 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ?0.2 ?0.15 ? 0.15 ?0.35 0.35 ? v ccio /2 ? sstl 135 1.283 1.35 1.45 0.2 ?0.2 v ref ? 0.135 v ccio /2 v ref + 0.135 tbd (1) tbd (1) v ref ?0.15 ? v ref + 0.15 sstl 125 1.19 1.25 1.31 tbd (1) ?tbd (1) v ccio /2 tbd (1) tbd (1) ?tbd (1) tbd (1) tbd (1) note to table 2?17 : (1) pending silicon characterization. table 2?18. differential hstl i/o standards for arria v devices? preliminary i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5 x v ccio ? 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.3 v ccio + 0.48 hsul-12 1.14 1.2 1.3 0.26 0.26 0.5 x v ccio ? 0.12 0.5 x v ccio 0.5 x v ccio +0.12 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.44 0.44 table 2?19. differential i/o standard specifications for arria v devices? preliminary (1) (part 1 of 2) i/o standard v ccio (v) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min max min typ max min typ max pcml (3)
2?14 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet power consumption altera offers two ways to estimate power consumption for a design?the excel-based early power estimator (epe) and the quartus ? ii powerplay power analyzer feature. 1 you typically use the interactive excel-based epe before designing the fpga to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . switching characteristics this section provides performance characteristics of arria v core and periphery blocks for commercial grade devices. these characteristics can be design ated as preliminary or final. preliminary characteristics are created usin g simulation results, process data, and other known parameters. the title of th ese tables show the designation as ?preliminary.? final numbers are based on actual sili con characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no preliminary designations on finalized tables. 2.5 v lvds 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.8 0.247 ? 0.6 1.125 1.25 1.375 ? 1.05 1.55 0.247 ? 0.6 1.125 1.25 1.375 rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 1.4 0.1 0.2 0.6 0.5 1.2 1.4 mini-lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 1.325 0.25 ? 0.6 1 1.2 1.4 lvpecl 2.375 2.5 2.625 300 ? ? 0.6 1.8 ? ? ? ? ? ? notes to table 2?19 : (1) the 1.4-v and 1.5-v pcml transceiver i/o standard spec ifications are described in ?transceiver performance specifications? on page 2?15 . (2) rl range: 90 ? rl ? 110 ? . (3) transmitter, receiver, and input reference clock pins of high-sp eed transceivers use the pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 2?20 and table 2?21 . table 2?19. differential i/o standard specifications for arria v devices? preliminary (1) (part 2 of 2) i/o standard v ccio (v) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min max min typ max min typ max
chapter 2: device datasheet for arria v devices 2?15 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet transceiver performance specifications this section describes transceiver performance specifications. table 2?20 and table 2?21 list the arria v transceiver specifications. table 2?20. transceiver specifications for arria v gx devices? preliminary (1) (part 1 of 3) symbol/ description conditions ?4 commercial speed grade ?5 commercial/industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.4 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl (2) , hcsl , and lvds input frequency from refclk input pins ? 27 ? 710 27 ? 710 27 ? 710 mhz duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 2000 200 ? 2000 200 ? 2000 mv spread-spectrum modulating clock frequency pci express ? (pcie ? ) 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0 to ?0.5% ?? 0 to ?0.5% ?? 0 to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1.1 (3) 1.1 (3) 1.1 (3) v v icm (dc coupled) hcsl i/o standard for the pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? ? transceiver clocks fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz avalon ? -memory- mapped (avalon-mm) phy management clock frequency < 150 mhz
2?16 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet receiver supported i/o standards 1.5 v pcml, 2.5 v pcml, lvpecl , and lvds data rate ? 611 ? 6553 611 ? 6553 611 ? 3125 mbps absolute v max for a receiver pin (4) ? ? ? 1.2 ? ? 1.2 ? ? 1.2 v absolute v min for a receiver pin ? ?0.4 ? ? ?0.4 ? ? ?0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration ? ? ? 2.2 ? ? 2.2 ? ? 2.2 v minimum differential eye opening at the receiver serial input pins (5) ?85??85??85??mv differential on-chip termination resistors 85- ? setting ? 85 ? ? 85 ? ? 85 ? ? 100- ? setting ? 100 ? ? 100 ? ? 100 ? ? 120- ? setting ? 120 ? ? 120 ? ? 120 ? ? 150- ? setting ? 150 ? ? 150 ? ? 150 ? ? differential and common mode return loss pcie (gen1 and gen2), gige, xaui, sdi, cpri, obsai compliant ? programmable ppm detector (6) ? 62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization ???4??4??4db programmable dc gain dc gain setting = 0 ?0 ??0 ??0 ? db dc gain setting = 1 ?3 ??3 ??3 ? db table 2?20. transceiver specifications for arria v gx devices? preliminary (1) (part 2 of 3) symbol/ description conditions ?4 commercial speed grade ?5 commercial/industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max
chapter 2: device datasheet for arria v devices 2?17 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet transmitter supported i/o standards 1.5 v pcml data rate ? 611 ? 6553 611 ? 6553 611 ? 3125 mbps v ocm ? ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85- ? setting ? 85 ? ? 85 ? ? 85 ? ? 100- ? setting ? 100 ? ? 100 ? ? 100 ? ? 120- ? setting ? 120 ? ? 120 ? ? 120 ? ? 150- ? setting ? 150 ? ? 150 ? ? 150 ? ? rise time (7) ? 30 ? 160 30 ? 160 30 ? 160 ps fall time (7) ? 30 ? 160 30 ? 160 30 ? 160 ps cmu pll supported data range ? 611 ? 6553 611 ? 6553 611 ? 3125 mbps transceiver-fpga fabric interface interface speed (single-width mode) ? 25 ? 187.50 25 ? 163.84 25 ? 156.25 mhz interface speed (double-width mode) ? 25 ? 163.84 25 ? 163.84 25 ? 156.25 mhz notes to table 2?20 : (1) speed grades shown in table 2?20 refer to the transceiver speed grade in the device ordering code. fo r more information about device ordering codes, refer to the overview for arri a v device family chapter. (2) differential lvpecl signal l evels must comply to the minimu m and maximum peak-to-peak differe ntial input voltage specified i n this table. (3) the reference clock common mo de voltage is equal to the v ccr_gxb power supply level. (4) the device cannot tolerate prolonged operation at this absolute maximum. (5) the differential eye opening speci fication at the receiver input pins assumes that you have disabled the receiver equalization feature. if you enable the receiver equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (6) the rate match fifo supports only up to 300 parts per million (ppm). (7) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. table 2?20. transceiver specifications for arria v gx devices? preliminary (1) (part 3 of 3) symbol/ description conditions ?4 commercial speed grade ?5 commercial/industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max
2?18 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?21. transceiver specifications for arria v gt devices? preliminary (1) (part 1 of 2) symbol/ description conditions ?5 industrial speed grade unit min typ max reference clock supported i/o standards 1.2 v pcml , 1.4 v pcml , 1.5 v pcml , 2.5 v pcml , differential lvpecl (2) , hcsl , and lvds input frequency from refclk input pins ? 27 ? 710 mhz duty cycle ? 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 2000 mv spread-spectrum modulating clock frequency pci express ? (pcie ? ) 30 ? 33 khz spread-spectrum downspread pcie ? 0 to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? v icm (ac coupled) ? 1.1 (3) v v icm (dc coupled) hcsl i/o standard for the pcie reference clock 250 ? 550 mv r ref ? ? 2000 1% ? ? transceiver clocks fixedclk clock frequency pcie receiver detect ? 125 ? mhz avalon-mm phy management clock frequency < 150 mhz receiver supported i/o standards 1.5 v pcml , 2.5 v pcml , lvpecl , and lvds data rate (6-gbps transceiver) ? 611 ? 6375 mbps data rate (10-gbps transceiver) ? 6.376 9.8304 10.3125 gbps absolute v max for a receiver pin (4) ???1.2v absolute v min for a receiver pin ? ?0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ???1.6v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration ???2.2v minimum differential eye opening at the receiver serial input pins (5) ?85??mv differential on-chip termination resistors 85- ? setting 85 ? 100- ? setting 100 ? 120- ? setting 120 ? 150- ? setting 150 ?
chapter 2: device datasheet for arria v devices 2?19 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet differential and common mode return loss pcie (gen1 and gen2), gige, xaui, sdi, cpri, obsai, sfi compliant ? programmable ppm detector (6) ? 62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm run length ? ? ? 200 ui programmable equalization ? ? ? 4 db programmable dc gain dc gain setting = 0 ? 0 ? db dc gain setting = 1 ? 3 ? db transmitter supported i/o standards 1.5 v pcml data rate (6-gbps transceiver) ? 611 ? 6375 mbps data rate (10-gbps transceiver) ? 6.376 9.8304 10.3125 gbps v ocm ? ? 650 ? mv differential on-chip termination resistors 85- ? setting ? 85 ? ? 100- ? setting ? 100 ? ? 120- ? setting ? 120 ? ? 150- ? setting ? 150 ? ? rise time (7) ? 30 ? 160 ps fall time (7) ? 30 ? 160 ps cmu pll supported data range ? 0.611 ? 10.3125 gbps transceiver-fpga fabric interface interface speed (80-bit mode) ? 25 ? 159.375 mhz interface speed (single-width mode) ? 25 ? 156.25 mhz interface speed (double-width mode) ? 25 ? 159.375 mhz notes to table 2?21 : (1) speed grades shown in table 2?21 refer to the transceiver speed gr ade in the device ordering code. fo r more information about device ordering codes, refer to the overview for arria v device family chapter. (2) differential lvpecl signal levels must comp ly to the minimum and maximum peak-to-peak differential input vo ltage specified in this table. (3) the reference clock common mo de voltage is equal to the v ccr_gxb power supply level. (4) the device cannot tolerate prolonged operation at this absolute maximum. (5) the differential eye opening speci fication at the receiver input pins assumes that you have disabled the receiver equalization feature. if you enable the receiver equalization feature, the receiver circuitry can tolerate a lower mi nimum eye opening, depending on the equalization level. (6) the rate match fifo supports only up to 300 ppm. (7) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. table 2?21. transceiver specifications for arria v gt devices? preliminary (1) (part 2 of 2) symbol/ description conditions ?5 industrial speed grade unit min typ max
2?20 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?22 and table 2?23 list the transceiver block jitter specification for arria v devices. table 2?22. transceiver block jitter specification for arria v gx devices? preliminary (part 1 of 4) symbol/ description conditions ?4 commercial speed grade ?5 commercial/ industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max cpri transmit jitter generation (1) total jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui cpri receiver jitter tolerance (1) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 > 0.66 ui deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 > 0.4 ui total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.55 > 0.55 > 0.55 ui obsai transmit jitter generation (2) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui
chapter 2: device datasheet for arria v devices 2?21 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet obsai receiver jitter tolerance (2) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 460 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 921.6 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1843.2 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 ui table 2?22. transceiver block jitter specification for arria v gx devices? preliminary (part 2 of 4) symbol/ description conditions ?4 commercial speed grade ?5 commercial/ industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max
2?22 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet serial rapidio ? (srio) transmit jitter generation (3) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ui srio receiver jitter tolerance (3) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 ui gige transmit jitter generation (4) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui table 2?22. transceiver block jitter specification for arria v gx devices? preliminary (part 3 of 4) symbol/ description conditions ?4 commercial speed grade ?5 commercial/ industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max
chapter 2: device datasheet for arria v devices 2?23 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet gige receiver jitter tolerance (4) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (5) deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.17 ? ? ? ? ? ? ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.35 ? ? ? ? ? ? ui notes to table 2?22 : (1) the jitter numbers for cpri are comp liant to the cpri specification v3.0. (2) the jitter numbers for ob sai are compliant to the o bsai rp3 specification v4.1. (3) the jitter numbers for srio are comp liant to the rapidio specification 1.3. (4) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. (5) the jitter numbers for hi gig are compliant to the ie ee802.3ae-2002 specification. table 2?22. transceiver block jitter specification for arria v gx devices? preliminary (part 4 of 4) symbol/ description conditions ?4 commercial speed grade ?5 commercial/ industrial speed grade ?6 commercial speed grade unit min typ max min typ max min typ max
2?24 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?23. transceiver block jitter specification for arria v gt devices? preliminary (part 1 of 3) symbol/ description conditions ?5 industrial speed grade unit min typ max sfi transmit jitter generation (1) deterministic jitter data rate = 9.8304, 10.3125 gbps pattern = prbs31 ? ? 0.1 ui total jitter ? ? 0.28 ui sfi receive jitter tolerance (1) 99% jitter tolerance data rate = 9.8304, 10.3125 gbps pattern = prbs31 >0.42 ui total jitter >0.70 ui cpri transmit jitter generation (2) total jitter e.6.hv, e.12.hv pattern = cjpat ??0.279? e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.35 ? deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.17 ? cpri receive jitter generation (2) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.65 > 0.65 deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.37 > 0.37 combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.55 > 0.55 obsai transmit jitter generation (3) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.35 ? deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6mhz pattern = cjpat ? ? 0.17 ?
chapter 2: device datasheet for arria v devices 2?25 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet obsai receiver jitter tolerance (3) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 jitter frequency = 460 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 jitter frequency = 921.6 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 jitter frequency = 1843.2 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 srio transmit jitter generation (4) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ui table 2?23. transceiver block jitter specification for arria v gt devices? preliminary (part 2 of 3) symbol/ description conditions ?5 industrial speed grade unit min typ max
2?26 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet srio receiver jitter tolerance (4) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 ui gige transmit jitter generation (5) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ui gige receiver jitter tolerance (5) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 ui higig transmit jitter generation (6) deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.17 ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.35 ui notes to table 2?23 : (1) the jitter numbers for sfi are co mpliant to sff-84 31 specification. (2) the jitter numbers for cpri are comp liant to the cpri specification v3.0. (3) the jitter numbers for ob sai are compliant to the o bsai rp3 specification v4.1. (4) the jitter numbers for srio are comp liant to the rapidio specification 1.3. (5) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. (6) the jitter numbers for hi gig are compliant to the ie ee802.3ae-2002 specification. table 2?23. transceiver block jitter specification for arria v gt devices? preliminary (part 3 of 3) symbol/ description conditions ?5 industrial speed grade unit min typ max
chapter 2: device datasheet for arria v devices 2?27 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), memory blocks and temperature sensing diode specifications. clock tree specifications table 2?24 lists the clock tree specifications for arria v devices. pll specifications table 2?25 lists the arria v pll specifications when operating in both the commercial junction temperature range (0 to 85c) and the industrial juncti on temperature range (?40 to 100c). table 2?24. clock tree performance for arria v devices? preliminary performance unit symbol ?c4 speed grade ?c5, i5 speed grade ?c6 speed grade global clock and regional clock 625 625 525 mhz peripheral clock 450 400 350 mhz table 2?25. pll specifications for arria v devices? preliminary (1) (part 1 of 3) symbol parameter min typ max unit f in input clock frequency (?4 speed grade) 5 ? 670 (2) mhz input clock frequency (?5 speed grade) 5 ? 622 (2) mhz input clock frequency (?6 speed grade) 5 ? 500 (2) mhz f inpfd integer input clock frequency to the pfd 5 ? 325 mhz f finpfd fractional input clock frequency to the pfd 50 ? tbd (1) mhz f vco pll vco operating range (?4 speed grade) 600 ? 1600 mhz pll vco operating range (?5 speed grade) 600 ? 1400 mhz pll vco operating range (?6 speed grade) 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock (?4 speed grade) ? ? 500 (3) mhz output frequency for internal global or regional clock (?5 speed grade) ? ? 500 (3) mhz output frequency for internal global or regional clock (?6 speed grade) ? ? 400 (3) mhz f out_ext output frequency for external clock output (?4 speed grade) ? ? 670 (3) mhz output frequency for external clock output (?5 speed grade) ? ? 622 (3) mhz output frequency for external clock output (?6 speed grade) ? ? 500 (3) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configphase time required to reconfigure phase shift ? ? tbd (1) ? t dyconfigclk dynamic configuration clock ? ? 100 mhz
2?28 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet t lock time required to lock from end-of-device configuration or deassertion of areset ?? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (8) ?4 ?mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (4) , (5) input clock cycle-to-cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle-to-cycle jitter (f ref < 100 mhz) ? ? +750 ps (p-p) t outpj_dc (6) period jitter for dedicated clock output (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outccj_dc (6) cycle-to-cycle jitter for dedicated clock output (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for dedicated clock output (f out < 100 mhz) ??tbd (1) mui (p-p) t outpj_io (6) , (9) period jitter for clock output on the regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for clock output on the regular i/o (f out < 100 mhz) ??tbd (1) mui (p-p) t outccj_io (6) , (9) cycle-to-cycle jitter for clock output on the regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for clock output on the regular i/o (f out < 100 mhz) ??tbd (1) mui (p-p) t outpj_dc_f period jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outccj_dc_f cycle-to-cycle jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outpj_io_f period jitter for clock output on the regular i/o in fractional mode ? ? tbd (1) ? t outccj_io_f cycle-to-cycle jitter for clock output on the regular i/o in fractional mode ? ? tbd (1) ? t casc_outpj_dc (6) , (7) period jitter for dedicated clock output in cascaded plls (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100 mhz) ??tbd (1) mui (p-p) t drift frequency drift after pfdena is disabled for a duration of 100 s ? ? 10 % table 2?25. pll specifications for arria v devices? preliminary (1) (part 2 of 3) symbol parameter min typ max unit
chapter 2: device datasheet for arria v devices 2?29 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet dsp block specifications table 2?26 lists the arria v dsp block performance specifications. dk bit bit number of delta sigma modulator (dsm) ? 24 ? bits k value numerator of fraction tbd (1) 8388608 tbd (1) ? f res resolution of vco frequency (f inpfd =100 mhz) ? 5.96 ? hz notes to table 2?25 : (1) pending silicon characterization. (2) this specification is limited in the qu artus ii software by the i/o m aximum frequency. the maximu m i/o frequency is differen t for each i/o standard. (3) this specification is limited by the lower of the two: i/o f max or f out of the pll. (4) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source < 120 ps. (5) f ref is fin/n when n = 1. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404 % confidence level). the output jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. the external memory interface clock output jitter sp ecifications use a different measurement method and are available in table 2?33 on page 2?35 . (7) the cascaded pll specification is only ap plicable with the fo llowing conditions: a. upstream pll: 0.59 mhz ? upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (8) high bandwidth pll settings are not supported in external feedback mode. (9) external memory interface clock output jitter specifications use a different measurement me thod, which are available in table 2?33 on page 2?35 . table 2?25. pll specifications for arria v devices? preliminary (1) (part 3 of 3) symbol parameter min typ max unit table 2?26. dsp block performance specifications for arria v devices? preliminary mode performance unit ?c4 speed grade ?c5, i5 speed grade ?c6 speed grade modes using one dsp block independent 9 x 9 multiplication 370 310 220 mhz independent 18 x 19 multiplication 370 310 220 mhz independent 18 x 18 multiplication 370 310 220 mhz independent 27 x 27 multiplication 310 250 200 mhz independent 18 x 25 multiplication 370 310 220 mhz independent 20 x 24 multiplication 370 310 220 mhz two 18 x 19 multiplier adder mode 370 310 220 mhz 18 x 18 multiplier added summed with 36-bit input 370 310 220 mhz modes using two dsp blocks complex 18 x 19 multiplication 370 310 220 mhz two 27 x 27 multiplier adder 310 250 200 mhz four 18 x 19 multiplier adder 370 310 220 mhz
2?30 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet memory block specifications table 2?27 lists the arria v memory block specifications. temperature sensing diode specifications table 2?28 lists the specifications for the arria v internal temperature sensing diode. table 2?27. memory block performance specifications for arria v devices? preliminary (1) , (2) memory mode resources used performance unit aluts memory c4 speed grade c5,i5 speed grade c6 speed grade mlab single port, all supported widths 0 1 500 450 400 mhz simple dual-port, all supported widths 0 1 500 450 400 mhz simple dual-port with read and write at the same address 0 1 400 350 300 mhz rom, all supported width ? ? 500 450 400 mhz m10k block single-port, all supported widths 0 1 400 350 285 mhz simple dual-port, all supported widths 0 1 400 350 285 mhz simple dual-port with the read-during-write option set to old data , all supported widths 0 1 315 275 240 mhz true dual port, all supported widths 0 1 400 350 285 mhz rom, all supported widths 0 1 400 350 285 mhz min pulse width (clock high time) ? ? 1,275 1,360 1,445 ps min pulse width (clock low time) ? ? 850 1,060 1,175 ps notes to table 2?27 : (1) to achieve the maximum memory block perfor mance, use a memory block clock that com es through global clock routing from an on -chip pll set to 50% output duty cycle. use the quartus ii software to report ti ming for this and other memo ry block clo cking schemes. (2) when you use the error detection cyclical redundancy check (crc) featur e, there is no degradation in f max . table 2?28. internal temperature sensing diode specifications for arria v devices? preliminary temperature range accuracy offset calibrated option sampling rate conversion time resolution minimum resolution with no missing codes ?40 to 100c 8c no frequency: 1mhz < 100 ms 8 bits 8 bits
chapter 2: device datasheet for arria v devices 2?31 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet periphery performance this section describes periphery performance and the high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the lvds high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. gpio standards such as 3.3- , 2.5-, 1.8-, and 1.5-v lvttl/lvcmos are capable of a typical 167 mhz and 1.2 lvcmos at 100 mhz interfacing frequency with a 10 pf load. 1 actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations base d on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specification table 2?29 lists high-speed i/o timing for arria v devices. table 2?29. high-speed i/o specifications for arria v devices? preliminary (1) , (2) , (3) (part 1 of 3) symbol conditions ?4 speed grade ?5 speed grade ?6 speed grade unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (5) 5 ? 625 5 ? 625 5 ? tbd mhz f hsclk_in (input clock frequency) single ended i/o standards (4) clock boost factor w = 1 to 40 (5) 5 ? 625 5 ? 625 5 ? tbd mhz f hsclk_in (input clock frequency) single ended i/o standards (3) clock boost factor w = 1 to 40 (5) 5? tbd 5? tbd 5?tbdmhz f hsclk_out (output clock frequency) ?5?625 (6) 5 ? 625 (6) 5?tbd (6) mhz
2?32 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet transmitter true differential i/o standards - f hsdr (data rate) serdes factor j = 3 to 10 (7) ? 1250 (7) ?1250 (7) ? 1050 mbps serdes factor j = 1 to 2, uses ddr registers (7) ? (7) (7) ? (7) (7) ? (7) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (8) serdes factor j = 4 to 10 (7) ?tbd (7) ?tbd (7) ?tbdmbps t x jitter - true differential i/o standards total jitter for data rate, 600 mbps - 1.25 gbps ? ? 160 ? ? 160 ? ? 160 ps total jitter for data rate, < 600 mbps ? ? 0.1 ? ? 0.1 ? ? 0.1 ui t x jitter - emulated differential i/o standards with three external output resistor network total jitter for data rate, 600 mbps ? 1.25 gbps ? ? tbd ? ? tbd ? ? tbd ps total jitter for data rate < 600 mbps ? ? tbd ? ? tbd ? ? tbd ui t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 200 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps tccs true differential i/o standards ? ? 150 ? ? 150 ? ? 150 ps emulated differential i/o standards ? ? 300 ? ? 300 ? ? 300 ps table 2?29. high-speed i/o specifications for arria v devices? preliminary (1) , (2) , (3) (part 2 of 3) symbol conditions ?4 speed grade ?5 speed grade ?6 speed grade unit min typ max min typ max min typ max
chapter 2: device datasheet for arria v devices 2?33 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet figure 2?1 shows the dpa lock time specifications with the dpa pll calibration option enabled. receiver true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 ? ? 1250 ? ? 1250 ? ? 1050 mbps f hsdr (data rate) serdes factor j = 3 to 10 (7) ? (9) (7) ? (9) (7) ? (9) mbps serdes factor j = 1 to 2, uses ddr registers (7) ? (7) (7) ? (7) (7) ? (7) mbps dpa mode dpa run length ? ? ? 10000 ? ? 10000 ? ? 10000 ui soft cdr mode soft-cdr ppm tolerance ? ? ? 300 ? ? 300 ? ? 300 ppm non dpa mode sampling window ? ? ? 300 ? ? 300 ? ? 300 ps notes to table 2?29 : (1) when j = 3 to 10, use the serializer/deserializer (serdes) block. (2) when j = 1 or 2, bypass the serdes block. (3) this applies to lvds source synchronous mode only. (4) this applies to dpa and soft-cdr modes only. (5) clock boost factor (w) is the ratio between the input data rate and the input clock rate. (6) this is achieved by usin g the lvds clock network. (7) the minimum specification depends on th e clock source (for example, the pll and cl ock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer and input register do not have a minimum toggle rate. (8) you must calculate the leftover timing ma rgin in the receiver by performing link ti ming closure analysis. you must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine th e leftover timing margin. (9) you can estimate the achievable maximum data rate for non-dpa mode by performing li nk timing closure analysis. you must cons ider the board skew margin, transmitter delay margin, and recei ver sampling margin to determine the maximum data rate supported. table 2?29. high-speed i/o specifications for arria v devices? preliminary (1) , (2) , (3) (part 3 of 3) symbol conditions ?4 speed grade ?5 speed grade ?6 speed grade unit min typ max min typ max min typ max figure 2?1. dpa lock time specification with dpa pll calibration enabled rx_dpa_locked rx_reset dpa lock time 256 data transitions 96 slow clock cycles 256 data transitions 256 data transitions 96 slow clock cycles
2?34 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?30 lists the dpa lock time specifications for arria v devices. figure 2?2 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to 1.25 gbps. table 2?31 lists the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to 1.25 gbps. table 2?30. dpa lock time specifications for arria v devices? preliminary (1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum spi-4 00000000001111111111 2 128 640 data transitions parallel rapid i/o 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions notes to table 2?30 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in this table appl ies to both co mmercial and in dustrial grades. (4) this is the number of repetition s for the stated training pattern to achieve the 256 data transitions. figure 2?2. lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate equal to 1.25 gbps lvds soft-cdr/dpa sinusoidal jitter tolerance specification f1 f2 f3 f4 jitter frequency (hz) jitter amphlitude (ui) 0.1 0.35 8.5 25 table 2?31. lvds soft-cdr/dpa sinusoidal jitter mask values for a data rate equal to 1.25 gbps? preliminary jitter frequency (hz) sinusoidal jitter (ui) f1 10,000 25.000 f2 17,565 25.000 f3 1,493,000 0.350 f4 50,000,000 0.350
chapter 2: device datasheet for arria v devices 2?35 switching characteristics february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet figure 2?3 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate less than 1.25 gbps. dqs logic block and memory output clock jitter specifications table 2?32 lists the dqs phase shift error for arria v devices. table 2?33 lists the memory output clock jitter specifications for arria v devices. figure 2?3. lvds soft-cdr/dpa sinusoidal jitter toler ance specification for a data rate less than 1.25 gbps 0.1 ui p-p baud/1667 20 mhz frequency sinusoidal jitter amplitude 20db/dec table 2?32. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for arria v devices? preliminary (1) , (2) number of dqs delay buffer ?c4 speed grade ?c5, i5 speed grade ?c6 speed grade unit 2575874ps notes to table 2?32 : (1) the numbers are preliminary pe nding silicon ch aracterization. (2) this error specification is the absolute maximum and minimum error. for example, skew on two dqs delay buffers in a ?4 speed grade is 58 ps or 29 ps. table 2?33. memory output clock jitter specification for arria v devices? preliminary (1) (part 1 of 2) parameter clock network symbol ?4 speed grade ?5 speed grade ?6 speed grade unit min max min max min max clock period jitter regional t jit(per) ?50 50 ?55 55 ?55 55 ps cycle-to-cycle period jitter regional t jit(cc) ?100 100 ?110 110 ?110 110 ps duty cycle jitter regional t jit(duty) ?50 50 ?82.5 82.5 ?82.5 82.5 ps clock period jitter global t jit(per) ?75 75 ?82.5 82.5 ?82.5 82.5 ps cycle-to-cycle period jitter global t jit(cc) ?150 150 ?165 165 ?165 165 ps
2?36 chapter 2: device datash eet for arria v devices switching characteristics arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet oct calibration block specifications table 2?34 lists the oct calibration block specifications for arria v devices. figure 2?4 shows the t rs_rt for dyn_term_ctrl and oe signals. duty cycle distorti on (dcd) specifications table 2?35 lists the worst-case dcd for arria v devices. duty cycle jitter global t jit(duty) ?75 75 ?90 90 ?90 90 ps note to table 2?33 : (1) the memory output clock jitter measurements are for 200 con secutive clock cycles, as specified in the je dec ddr2/ddr3 sdram standard. table 2?33. memory output clock jitter specification for arria v devices? preliminary (1) (part 2 of 2) parameter clock network symbol ?4 speed grade ?5 speed grade ?6 speed grade unit min max min max min max table 2?34. oct calibration block specifications for arria v devices? preliminary symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for r s oct /r t oct calibration ? 1000 ? cycles t octshift number of octusrclk clock cycles required for oct code to shift out ? 32 ? cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between r s oct and r t oct ?2.5? ns figure 2?4. timing diagram for dyn_term_ctrl and oe signals table 2?35. worst-case dcd on arria v i/o pins? preliminary symbol ?c4 speed grade ?c5,i5 speed grade ?c6 speed grade unit min max min max min max output duty cycle 45 55 45 55 45 55 % t rs_rt t rs_rt dyn_term_ctrl oe tristate rx rx tristate
chapter 2: device datasheet for arria v devices 2?37 configuration specification february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet configuration specification this section provides configuration specifications and timing for arria v devices. these characteristics can be design ated as preliminary or final. preliminary characteristics are created usin g simulation results, process data, and other known parameters. the title of th ese tables show the designation as ?preliminary.? final numbers are based on actual sili con characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no designations on finalized tables. por specifications table 2?36 lists the specifications for fast an d standard por for arria v devices. jtag configuration timing table 2?37 lists the jtag timing parameters and values for arria v devices. table 2?36. fast and standard por delay specification for arria v devices (1) por delay minimum (ms) maximum (ms) fast (2) 412 standard (3) 100 300 notes to table 2?36 : (1) select the por delay based on the msel setting as described in the ?configuration schemes for arria v devices? table in the configuration, design security, and remo te system upgrades in arria v devices chapter. (2) when the porsel signal is high , the device is in fast por delay. (3) when the porsel signal is low , the device is in standard por delay. table 2?37. jtag timing parameters and values for arria v devices? preliminary symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (1) ns t jpzx jtag port high impedance to valid output ? 14 (1) ns t jpxz jtag port valid output to high impedance ? 14 (1) ns note to table 2?37 : (1) a 1-ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v.
2?38 chapter 2: device datash eet for arria v devices configuration specification arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet fpp configuration timing this section describes the fast passive para llel (fpp) configuratio n timing parameters for arria v devices. dclk-to-data[] ratio (r) for fpp configuration fpp configuration requires a different dclk -to- data[] ratio when you turn on encryption or the compression feature. table 2?38 lists the dclk -to- data[] ratio for each combination. fpp configuration timing when dclk to data[] = 1 figure 2?5 shows the timing waveform for a fpp configuration when using a max ? ii device as an external host. this ti ming waveform shows timing when the dclk -to- data[] ratio is 1. 1 when you enable decompression or the design security feature, the dclk -to- data[] ratio varies for fpp x8 and fpp x16. for the respective dclk -to- data[] ratio, refer to table 2?38 . table 2?38. dclk-to-data[] ratio for arria v devices (1) configuration scheme encryption compression dclk-to-data[] ratio (r) fpp (8-bit wide) off off 1 on off 1 off on 2 on on 2 fpp (16-bit wide) off off 1 on off 2 off on 4 on on 4 note to table 2?38 : (1) depending on the dclk -to- data[] ratio, the host must send a dclk frequency that is r times the data[] rate in byte per second (bps) or word pe r second (wps). for example, in fpp x16 where the r is 2, the dclk frequency must be 2 times the data[] rate in wps.
chapter 2: device datasheet for arria v devices 2?39 configuration specification february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet figure 2?5. dclk-to-data[] fpp configuration timing waveform when the ratio is 1 (1) notes to figure 2?5 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic-high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the arria v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) for fpp x16, use data[15..0] . for fpp x8, use data[7..0] . data[15..0] are available as a user i/o pin afte r configuration. the state of this pin depends on the dual-purpose pin settings. (6) to ensure a successful configur ation, send the entire configurat ion data to the arria v device. conf_done is released high when the arria v device receives all the configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (7) after the option bit to enable the init_done pin is configured into the device, the init_done goes low. nconfig nstatus (2) conf_done (3) dclk data[15..0] user i/o init_done word 0 word 1 word 2 word 3 t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (7) (4) user mode word n-2 word n-1 word n (6)
2?40 chapter 2: device datash eet for arria v devices configuration specification arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?39 lists the timing paramete rs for arria v devices for fpp configuration when the dclk -to- data[] ratio is 1. table 2?39. dclk-to-data[] fpp timing parameters for arria v devices when the ratio is 1? preliminary (1) symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (2) s t cf2st1 nconfig high to nstatus high ? 1506 (3) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency (fpp x8/ x16) ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (4) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?39 : (1) use these timing pa rameters when the dclk -to- data[] ratio is 1. to find the dclk -to- data[] ratio for your system, refer table 2?38 on page 2?38 . (2) you can obtain this value if you do not delay configuratio n by extending the nconfig or the nstatus low pulse width. (3) you can obtain this value if you do not delay configuration by externally holding the nstatus low. (4) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
chapter 2: device datasheet for arria v devices 2?41 configuration specification february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet fpp configuration timing when dclk to data[] > 1 figure 2?6 shows the timing waveform for a fpp configuration when using a max ii device or microprocessor as an external host. this waveform shows timing when the dclk -to- data[] ratio is more than 1. figure 2?6. fpp configuration timing waveform when the dclk-to-data[] ratio is >1 (1) , (2) notes to figure 2?6 : (1) to find the dclk -to- data[] ratio for your system, refer table 2?38 on page 2?38 . (2) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reco nfiguration cycle begins. (3) after power up, the arria v device holds nstatus low for the time as specified by the por delay. (4) after power up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) ?r? denotes the dclk -to- data[] ratio. for the dclk -to- data[] ratio based on the decompression an d the design security feature enable settings, refer to table 2?38 on page 2?38 . (7) if needed, pause dclk by holding it low. when dclk restarts, the external host must provide data on the data[15..0] pins prior to sending the first dclk rising edge. (8) to ensure a successful configurat ion, send the entire configurat ion data to the arria v device. conf_done is released high after the arria v device receives all the configuratio n data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (9) after the option bit to enable the init_done pin is configured into the device, the init_done goes low. nconfig nstatus (3) conf_done (4) dclk (6) data[15..0] (8) user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck high-z user mode 12 r 12 r 12 word 0 word 1 word 3 1 t dsu t dh status t dh t ch t cl t clk word ( n -1) (7) (8) (9) (5) user mode r word n
2?42 chapter 2: device datash eet for arria v devices configuration specification arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?40 lists the timing parameters for arria v devices when the dclk -to- data[] ratio is more than 1. table 2?40. dclk-to-data[] fpp timing parameters for arria v devices when the ratio is >1? preliminary (1) symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (2) s t cf2st1 nconfig high to nstatus high ? 1506 (3) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 3 x 1/f dclk ?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency (fpp x8/ x16) ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (4) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?40 : (1) use these timing parameters wh en you use decompression and th e design security features. (2) this value can be obtained if you do not delay configuration by extending the nconfig or nstatus low pulse width. (3) this value can be obtained if you do no t delay configuration by externally holding nstatus low. (4) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
chapter 2: device datasheet for arria v devices 2?43 configuration specification february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet as configuration timing figure 2?7 shows the timing waveform for the acti ve serial (as) x1 mode and as x4 mode configuration timing. table 2?41 lists the timing parameters for as x1 and as x4 configurations in arria v devices. figure 2?7. as configuration timing notes to figure 2?7 : (1) the as scheme supports stan dard and fast por delay (t por ). for t por delay information, refer to the ?p or delay specification? section in the configuration, design security, and re mote system upgrad es in arria v devices chapter. (2) if you are using as x4 mode, this signal re presents the as_data[3..0] and epcq sends in 4-bits of data for each dclk cycle. (3) the initialization clock can be from the internal oscillator or clkusr pin. (4) after the option bit to enable the init_done pin is configured into the device, the init_done goes low. read address bit n - 1 bit n bit 1 bit 0 t cd2um nstatus nconfig conf_done ncso dclk as_data0/asdo as_data1 (2) init_done (4) user i/o user mode t por t dh t su t co (1) (3) table 2?41. as timing parameters for as x1 and x4 configurations in arria v devices? preliminary (1) , (2) symbol parameter minimum maximum unit t co dclk falling edge to the as_data0 / asdo output ? 4 s t su data setup time before the rising edge on dclk 1.5 ? ns t h data hold time after the rising edge on dclk 0?ns t cd2um conf_done high to user mode 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?41 : (1) the minimum and maximum numbers apply onl y if you choose the internal oscillator as the clock so urce for initializing the de vice. (2) the t cf2cd , t cf2st0 , t cfg , t status , and t cf2st1 timing parameters are iden tical to the timing paramete rs for ps mode listed in table 2?43 on page 2?45 .
2?44 chapter 2: device datash eet for arria v devices configuration specification arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?42 lists the internal clock frequency sp ecification for the as configuration scheme. ps configuration timing figure 2?8 shows the timing waveform for a pass ive serial (ps) configuration when using a max ii device or microp rocessor as an external host. table 2?42. dclk frequency specification in the as configuration scheme? preliminary (1) , (2) minimum typical maximum unit 5.3 7.9 12.5 mhz 10.6 15.7 25.0 mhz 21.3 31.4 50.0 mhz 42.6 62.9 100.0 mhz notes to table 2?42 : (1) this applies to the dclk frequency sp ecification when using the in ternal oscillator as the configuration clock source. (2) the as multi-device configur ation scheme does not support dclk frequency of 100 mhz. figure 2?8. ps configuration timing waveform (1) notes to figure 2?8 : (1) the beginning of this waveform shows the device in user mo de. in user mode, nconfig , nstatus , and conf_done are at logic hi gh levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the arria v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) data0 is available as a user i/o pin after configuration. the stat e of this pin depends on the dual-purpose pin settings in the device and pins option . (6) to ensure a successful configurat ion, send the entire configurat ion data to the arria v device. conf_done is released high after the arria v device receives all the configuratio n data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (7) after the option bit to enable the init_done pin is configured into the device, the init_done goes low. nconfig nstatus (2) conf_done (3) dclk data0 user i/o init_done (7) bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (4) (6)
chapter 2: device datasheet for arria v devices 2?45 configuration specification february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet table 2?43 lists the ps timing para meter for arria v devices. table 2?43. ps timing parameters for arria v devices? preliminary symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (1) s t cf2st1 nconfig high to nstatus high ? 1506 (2) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (3) 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?43 : (1) you can obtain this value if you do not delay configuratio n by extending the nconfig or nstatus low pulse width. (2) you can obtain this value if you do no t delay configuration by externally holding nstatus low. (3) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
2?46 chapter 2: device datash eet for arria v devices configuration specification arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet remote system upgrades ci rcuitry timing specification table 2?44 lists the timing parame ter specifications for the remote system upgrade circuitry. user watchdog internal osc illator frequency specification table 2?45 lists the frequency specifications for the user watchdog internal oscillator. table 2?44. remote system upgrade circuitry timing specification parameter minimum maximum unit t max_ru_clk (1) ?40mhz t ru_nconfig (2) 250 ? ns t ru_nrstimer (3) 250 ? ns notes to table 2?44 : (1) this clock is user-supplied to the remote system upgrade circuitry. if you are using the altremote_update megafunction, the clock user-supplied to the altremote_ update megafunction must meet this specification. (2) this is equivalent to strobing the reconfiguration input of the altremote_update megafunction high for the minimum timing specification. for more information, refer to the ?remote system upgrade state machine? section in the device interfaces and integratio n basics for arria v devices chapter. (3) this is equivalent to st robing the reset timer input of the altr emote_update megafunction high for the minimum timing specification. for more information, refer to the ?user watchdog timer? section in the device interfaces and integration basics for arria v devices chapter. table 2?45. user watchdog internal oscillator frequency specifications? preliminary minimum typical maximum unit 5.3 7.9 12.5 mhz
chapter 2: device datasheet for arria v devices 2?47 i/o timing february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the li nk timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. f you can download the excel-based i/o timing spreadsheet from the arria v devices literature webpage. programmable ioe delay table 2?46 lists the arria v ioe pr ogrammable delay settings. programmable output buffer delay table 2?47 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. table 2?46. ioe programmable delay for arria v devices (1) parameter available settings minimum offset fast model slow model unit industrial commercial c4 c5, i5 c6 tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns note to table 2?46 : (1) pending the quartus ii software extraction. table 2?47. programmable output buffer delay? preliminary (1) , (2) symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps notes to table 2?47 : (1) pending the quartus ii software extraction. (2) you can set the progra mmable output buffer de lay in the quartus ii software by setting the output buffer delay control assignment to either positive, negati ve, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment.
2?48 chapter 2: device datash eet for arria v devices glossary arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet glossary table 2?48 lists the glossary for this chapter. table 2?48. glossary table (part 1 of 4) letter subject definitions a b c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block?maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block?maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g h i ?? single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p - n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p - n = 0 v v cm
chapter 2: device datasheet for arria v devices 2?49 glossary february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet j j high-speed i/o block?deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k l m n o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? rr l receiver differential input discrete resistor (external to the arria v device). table 2?48. glossary table (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n pfd switchover delta sigma modulator vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c17 4
2?50 chapter 2: device datash eet for arria v devices glossary arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet s sampling window (sw) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position in the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for the sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including the t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block?duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and the data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fall signal high-to-low transition time (80?20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input t outpj_io period jitter on the gpio driven by a pll t outpj_dc period jitter on the dedicated clock output driven by a pll t rise signal low-to-high transition time (20?80%) u ?? table 2?48. glossary table (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
chapter 2: device datasheet for arria v devices 2?51 document revision history february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet document revision history table 2?49 lists the revision history for this chapter. v v cm(dc) dc common mode input voltage. v icm input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage v ih(dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage v il(dc) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block?clock boost factor x, y, z ?? table 2?48. glossary table (part 4 of 4) letter subject definitions table 2?49. document revision history date version changes february 2012 1.3 updated table 2?1 . updated transceiver-fpga fabric interface rows in table 2?20 . updated v ccp description. december 2011 1.2 updated table 2?1 , and table 2?3 . november 2011 1.1 updated table 2?1 , table 2?19 , table 2?26 , and table 2?36 . added table 2?5 . added figure 2?4 . august 2011 1.0 initial release.
2?52 chapter 2: device datash eet for arria v devices document revision history arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet
february 2012 altera corporation arria v device handbook volume 1: device overview and datasheet additional information this chapter provides additional info rmation about the document and altera. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature nontechnical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicate keyboard keys and menu names. for example, the delete key and the options menu. ?subheading title? quotation marks indicate references to sections in a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information typographic conventions arria v device handbook february 2012 altera corporation volume 1: device overview and datasheet courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h a question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning

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